1. Field of the Invention
The present invention relates to a differential amplifier, and in particular to a differential amplifier having a resistance load type differential pair in an integrated circuit.
The differential amplifier is utilized in a large number of electric circuits regardless of technical fields, and many of these electric circuits are utilized in an integrated form such as an IC or LSI.
As for circuit parts such as transistors, only discrete parts which had fulfilled the specification have been shipped. Therefore, circuit designs for the discrete parts have been made possible without much consideration of manufacturing process conditions because of little individual differences between the parts. Only consideration focused on circumferential variations such as temperature in use had to be made. However, as demands for speedup and space saving increase in the market, the integration of the circuits has been urged.
Integrated circuit designs, considering a manufacturing yield, require circuit designs allowing individual differences between lots depending on manufacturing process conditions.
Furthermore, minute machining for IC's (or LSI's) has been energetically advanced in recent years for the purpose of the speedup and cost reduction. Along with this, source voltages of electric circuits tend to decrease. This is because a malfunction caused by an occurrence of a leak current or the like due to an insulator destruction with a high voltage is prevented since the thickness of an oxide film of a gate or the like is thinned by the minute machining, taking a CMOS transistor as an example.
Therefore, a direct current design at a low voltage considering variations of circumferential and manufacturing process conditions has become more and more difficult. Particularly, it is required for a differential amplifier in many cases, especially in such a case as performing a feed forward control, that the gain variation is small against the variations of the circumferential and manufacturing process conditions.
2. Description of the Related Art
For a bias current of a differential amplifier, a current source (constant current source) 1 as shown in FIG. 8 for suppressing a current amount variation caused by variations of circumferential conditions, a current source 2 as shown in FIG. 9 for suppressing an internal resistance variation in an amplifier having a resistance load type differential pair and suppressing a limiter amplitude variation, or. a current source 3 as shown in FIG. 10 for suppressing a small signal gain variation in an amplifier having a resistance load type differential pair has been so far used individually according to the object of use. Hereinafter, the respective operations will be described taking a CMOS transistor as an example.
Firstly, the current source (constant current source) 1 shown in FIG. 8 will be described. It is often the case that an integrated circuit IC1 internally has a reference constant voltage source S1 utilizing PN semiconductor junctions with an output voltage V.sub.BGR to the extent of 1.2V which is called a band gap reference (BGR), having an extremely little variation dependency on the variations of the circumferential and manufacturing process conditions.
This reference voltage V.sub.BGR is dropped by a voltage divider rl to an allowable input range of an operational amplifier OA1 to make a reference potential V.sub.ref thereof. The operational amplifier OA1 controls a transistor M11 so that a potential R.sub.c.times.I.sub.c by a current I.sub.c which flows through a resistor r2 (resistance R.sub.c) which is externally connected to the integrated circuit IC1 is equal to the reference potential V.sub.ref. Thus, the current source 1 of FIG. 8 outputs a current determined by the following equation: EQU I.sub.c =V.sub.ref /R.sub.c Eq. (1)
It is to be noted that the reference voltage V.sub.ref has a little dependency on condition variations since it is generated from the voltage V.sub.BGR which has little dependency on the condition variations by a voltage division ratio of the resistor r1, which is constant even if the resistance varies. Also, the reference resistor r2 has a very little temperature dependency of less than.+-.several 100 ppm/.degree. C. because of an externally connected component.
Since Eq. (1) includes no element depending on the source, no dependency on a source voltage arises as long as the operational amplifier OA1 or the like has a range of source voltage where a normal operation is enabled. Therefore, a constant current I.sub.c determined by Eq. (1) which has a very little dependency on the condition variations can be obtained. The current I.sub.c is reproduced as a current I.sub.d by a current mirror CM1 which is composed of transistors M12, M14, M13, and M15 so as to be provided as a bias current I.sub.s to a differential pair of an amplifier (not shown) of a resistance load type.
On the other hand, it is generally known that a small signal gain G of an amplifier having a resistance load type differential pair is expressed by the following equation: EQU G=R.times. .beta..times. I.sub.s Eq. (2)
[R: load resistance, .beta.: gain coefficient of MOS-FET, I.sub.s : bias current value] PA1 [.beta.=.mu..multidot.C.sub.ox.multidot.W/L (.mu.: electron mobility, C.sub.ox : gate oxide film capacity, W: gate width, L: gate length)] PA1 Low voltage operation (minute machining of manufacturing process) PA1 High speed operation (enhancement of signal band) PA1 [G.sub.typ =R.sub.typ.times. .beta..sub.typ.times. I.sub.s =constant, .DELTA..sub.G : small signal gain variation] EQU V/V.sub.typ =1.+-..DELTA..sub.Vl =[.alpha.+(1-.alpha.)/{(1.+-..DELTA.r).times.(1.+-..DELTA.B)}] Eq. (28)
Namely, supposing that an input potential difference of the differential pair is v.sub.in, an output signal amplitude of v.sub.in.times.G is generated between a load resistor (not shown) and the differential pair.
Also, a limiter amplitude V.sub.lm (V.sub.in.times.G.ltoreq.V.sub.lm) which is a maximum output amplitude generated between the load resistor and the differential pair is expressed by the following equation: EQU V.sub.lm =R.times.I.sub.s Eq. (3)
In view of an integrated circuit having a resistance element in the manufacturing process, the load resistance R and the gain coefficient .beta. vary as the circumferential and manufacturing process conditions vary as given by the following equations: EQU R=R.sub.typ (1.+-..DELTA..sub.r) Eq. (4) EQU .beta.=.beta..sub.typ (1.+-..DELTA..sub.B) Eq. (5)
where R.sub.typ and .beta..sub.typ indicate design values in a circumferential condition which is most frequently used and in a manufacturing process condition (typical condition) which is best achieved, and .DELTA..sub.r and .DELTA..sub.B indicate variation amounts when the values are off the circumferential and manufacturing conditions.
It is to be noted that upon a circuit design, .DELTA..sub.r and .DELTA..sub.B are preliminary given to each manufacturing process used from conditions such as a working temperature range and a manufacturing yield according to the design specification. In addition, although .DELTA..sub.r and .DELTA..sub.B have a correlation with the temperature variation in some manufacturing processes, it may be generally considered that they vary independently of the condition variations.
Accordingly, the small signal gain G and the limiter amplitude V.sub.lm of the amplifier having the resistance load type differential pair given by Eqs. (2) and (3) are given by the following equations in consideration of the condition variations. EQU G=R.sub.typ.times. .beta..sub.typ.times. I.sub.s.times.(1.+-..DELTA..sub.r).times.(1.+-..DELTA..sub.B).sup.0.5 Eq. (6) EQU V.sub.lm =R.sub.typ.times.I.sub.s.times.(1.+-..DELTA..sub.r) Eq. (7)
Therefore, when the current I.sub.d generated by the constant current source 1 in FIG. 8 is provided as the bias current I.sub.s (=constant) to the differential pair, Eqs. (6) and (7) can be respectively rewritten as the following equations: EQU G=G.sub.typ.times.(1.+-..DELTA..sub.r).times.(1.DELTA..sub.B).sup.0.5 Eq. (8) EQU [G.sub.typ =R.sub.typ.times. .beta..sub.typ.times. I.sub.s =constant] EQU V.sub.lm =V.sub.typ.times.(1.+-..DELTA..sub.r) Eq. (9) EQU [V.sub.typ =R.sub.typ.times.I.sub.s =constant]
Namely, it is found that both of the small signal gain G and the limiter amplitude V.sub.lm vary with the condition variations.
This kind of current source is mostly used as a bias for a resistance load type differential pair utilizing an external resistor in a manufacturing process for such as a part of a bipolar and a gallium-arsenic series which has no resistance element excluding considerations of resistance variation or for a pair having an active load type differential pair which utilizes an internal resistor of a transistor and which is not suitable for an analog amplification due to an extremely high gain in many cases.
The current source 2 shown in FIG. 9 for suppressing or compensating an internal resistance variation in an amplifier (not shown) having a resistance load type differential pair will now be described.
This resistance variation suppressing type current source 2 can be provided by replacing the external reference resistor r2 in FIG. 1 with an internal resistor in an integrated circuit IC2 for the suppressing resistor of the constant current source.
Therefore, in this resistance variation suppressing type current source 2, an operational amplifier OA2 controls a transistor M21 so that a voltage drop=R.sub.ic.times.I.sub.r by a current I.sub.r flowing through a reference resistor r3 of a resistance R.sub.ic within the integrated circuit IC2 is equal to the reference potential V.sub.ref. Thus, the current source 2 of FIG. 9 outputs a current determined by the following equation: EQU I.sub.r =V.sub.ref /R.sub.ic Eq. (10)
It is to be noted that the reference potential V.sub.ref has a little dependency on condition variations. Since Eq. (10) includes no element depending on the source, no dependency on a source voltage arises as long as the operational amplifier OA2 or the like has a range of source voltage where a normal operation is enabled. However, R.sub.ic presents a variation similar to Eq. (4) against the condition variations as expressed by the following equation: EQU R.sub.ic =r.sub.typ (1.DELTA..sub.r) Eq. (11)
When the current I.sub.r in the above-mentioned Eq. (10) by the resistance variation suppressing type current source 2 is provided as the bias current I.sub.s to the differential pair, the following equation is given: EQU I.sub.r =I.sub.s /(1.+-..DELTA..sub.r) Eq. (12) EQU [I.sub.s =(kV.sub.ref /r.sub.typ =constant), EQU k: constant determined by current mirror ratio and the like]
Accordingly, by using Eqs. (2) and (3), the small signal gain G and the limiter amplitude V.sub.lm of the differential amplifier are respectively expressed by the following equations: EQU G=R.times. .beta..times. I.sub.r =G.sub.typ.times.(1.+-..DELTA..sub.r).sup.0.5.times.(1.+-..DELTA..sub.B). sup.0.5 Eq. (13) EQU [G.sub.typ =R.sub.typ.times. .beta..sub.typ.times. I.sub.s =constant] EQU V.sub.lm =R.times.I.sub.r =V.sub.typ (=constant) Eq. (14) EQU [V.sub.typ =R.sub.typ.times.I.sub.s =constant]
Namely, it is understood that while the small signal gain G varies with the condition variation, the limiter amplitude V.sub.lm is kept constant. This kind of current source is often used as a bias for the last staged differential pair (slicer circuit) of an analog amplifier since it keeps the output signal amplitude constant.
The current source 3 shown in FIG. 10 for suppressing a small signal gain variation in an amplifier having a resistance load type differential pair will now be described. In Eq. (2), suppressing the variation of the small signal gain G can require the current value I.sub.s of the bias current source to vary in proportion to 1/R.sup.2 and 1/.beta. to cancel the variations of R and .beta.. In FIG. 10, it is supposed that a suppressing transistor M32 has a gate whose width is "N" times as wide as that of a suppressing transistor M31, while otherwise both are the same. At this time, currents I.sub.31 and I.sub.32 which respectively flow through the transistors M31 and M32 are approximately expressed as the following equations: EQU I.sub.31 =(.beta./2).times.(Vgs.sub.31 -Vt).sup.2 Eq. (15) EQU I.sub.32 =(N.beta./2).times.(Vgs.sub.32 -Vt).sup.2 Eq. (16)
[Vgs.sub.31, Vgs.sub.32 : voltages between the gate and source of M31 and M32,
Vt: threshold value of CMOS transistor]
Potentials at points A and B in FIG. 10 are dropped to an appropriate voltage through a source follower 11 composed of transistors M3-M10 including a current mirror CM32 and controlled to be mutually equal by an operational amplifier OA3 and transistors M31-M34. Since a potential difference between Vgs.sub.31 and Vgs.sub.32 is applied across the ends of a suppressing resistor r4 (resistance r), the following equation can be obtained. EQU Vgs.sub.31 -Vgs.sub.32 =r.times.I.sub.32.times. (2I.sub.31 /.beta.)- {2I.sub.32 /(N.beta.)} Eq. (17)
Also, since the points A and B have the same potential, the currents I.sub.31 and I.sub.32 which respectively flow through R31 and R32 of the same resistance have the same value. Accordingly, a current I.sub.33 flowing through a current source transistor M33 is expressed with a calculation constant k.sub.1, a variation component of the resistance r of the resistor r4, and a variation component of the gain coefficient .beta. using Eq. (17) as given by the following equation: (It is to be noted that another solution of Eq. (17), which is I.sub.33 =0, lets a start-up circuit 10 composed of transistors M35 and M36 flow a start-up current I.sub.ST through the transistors M35 and M36 by a current mirror CM31, thereby prohibiting the state where no current flows through the suppressing transistors M31 and M32.) EQU I.sub.33 =I.sub.31 +I.sub.32 (=2I.sub.32)=((4/(r.sup.2.beta.))(1-1/ N).sup.2 =k.sub.1 /{R.sub.typ.sup.2 (1.+-..DELTA..sub.r).sup.2.times..beta..sub.typ (1.+-..DELTA..sub.B)} Eq. (18)
Accordingly, the current expressed by Eq. (18) varying in proportion to 1/R.sup.2 and 1/.beta. is used as a bias current I.sub.g for a differential amplifier (not shown) by a current mirror (a current mirror CM33 having a ratio k.sub.2 and composed of the operational amplifier OA3 and transistors M31-M34, M37, and M38) given by the following equation: EQU I.sub.g =k.sub.2.times.I.sub.33 =I.sub.s /{(1.+-..DELTA..sub.r).sup.2.times.(1.+-..DELTA..sub.B)} Eq. (19) EQU [I.sub.s =4(1-1/ N).sup.2 /{r.sub.typ.sup.2.times..beta..sub.typ }=constant]
Thus, the small signal gain G and the limiter amplitude V.sub.lm are respectively expressed by the following equations from Eqs. (2) and (3): EQU G=R.times. .beta..times. I.sub.g =G.sub.typ (=constant) Eq. (20) EQU [G.sub.typ =R.sub.typ.times. .beta..sub.typ.times. I.sub.s =constant] EQU V.sub.lm =R.times.I.sub.g =V.sub.typ /{(1.+-..DELTA..sub.r).times.(1.+-..DELTA..sub.B)} Eq. (21) EQU [V.sub.typ =R.sub.typ.times.I.sub.s =constant]
Namely, while the limiter amplitude V.sub.lm varies with condition variations, the small signal gain G is kept constant. Moreover, since Eqs. (19)-(21) include no element depending on the source, no dependency on a source voltage arises as long as the operational amplifier OA3 or the like has a range of source voltage where a normal operation is enabled.
It is to be noted that since the arrangement example of FIG. 10 performs a suppression of variation for an N-type differential pair, a suppression of variation for a P-type differential pair can be performed in the same arrangement by replacing the N-type transistor with the P-type, the source with the earth, the earth with the source, and the like.
A resistance load type differential pair using this kind of current source as a bias circuit can provide a linear output amplitude in response to an input amplitude even under the conditions varying. Therefore, it is frequently used in a circuit, where an analog linear amplification of a small signal is regarded as important, such as a circuit for performing a separation of S/N (Signal/Noise), i.e. a comparison of a constant identification potential with a signal amplitude of V.sub.in-pp.times.G after the amplification.
It is important for such an analog integrated circuit design to fulfill the following requirements:
Requirement 1:
Requirement 2:
Concerning the "Requirement 1", as the minute machining of IC's or LSI's has made a further progress in recent years for the purpose of the cost reduction, the source voltage of an integrated circuit has been reduced than before to the extent of e.g. 3V. Although being preferable from a viewpoint of low power consumption, this has resulted in much burden to the direct current design not requiring much consideration therefor.
As an example, this has become remarkable especially in case of an analog linear amplification. In the analog linear amplification, it is important for the purpose of suppressing the signal deterioration caused by wave distortions and the like to use all of the transistors composing the differential pair in the saturating operation, that is to use them over a range of voltage between the drain and the source where the variation of the current therebetween the drain and the source is extremely small with respect to the variation of the voltage Vds therebetween in case of CMOS transistors.
The direct current designs for the resistance load type differential pair are applied to the differential pair itself and the input/output levels of the differential pair.
This will be described hereinafter referring to FIG. 11. Firstly, the following equation is given for the differential pair itself. EQU V.sub.dd (source voltage).gtoreq.R.times.I.sub.s +V.sub.ds-min (differential pair)+V.sub.ds-min (bias source) Eq. (22)
[V.sub.ds-min : minimum required voltage between drain and source for saturating operation]
Moreover, a relation of the following equation is required for an input signal level of differential pairs 41 and 43. EQU V.sub.in-min (minimum signal input voltage).gtoreq.V.sub.t (differential pair)+V.sub.ds-min (bias source) Eq. (23)
[V.sub.t : threshold potential of transistor]
In the above Eq. (23), the purpose of considering V.sub.t of the differential pair is to suppress the wave distortions by realizing an instantaneous output response to an input since little current flows through the transistor at the voltage of V.sub.t or below.
Also, concerning the minimum signal input voltage V.sub.in-min, an amplifier often employs multi-staged differential pairs 41 and 43 as shown in FIG. 11 which are mutually connected with a buffer such as a source follower 45 or an emitter follower. Accordingly, an input level between each differential pair (differential pair 43) after the first stage is expressed by the following equation:
V.sub.in-min =V.sub.dd -R.times.I.sub.s -V.sub.gs (output voltage drop of source follower) Eq. (24)
Accordingly, the following equation is given by substituting Eq. (23) for Eq. (24). EQU V.sub.dd -R.times.I.sub.s.times.V.sub.gs (source follower).gtoreq.V.sub.t (differential pair)+V.sub.ds-min (bias source) V.sub.dd.gtoreq.R.times.I.sub.s +V.sub.gs (source follower)+V.sub.t (differential pair)+V.sub.ds-min (bias source) Eq. (25)
Accordingly, since the "Requirement 1" means that the upper limit V.sub.dd becomes low in Eqs. (22) and (25) expressing the conditions for the direct current design, the limiter amplitude R.times.I.sub.s (see Eq. (3)) is restricted in Eq. (25), thereby making the direct current design difficult.
Also, the enhancement of the signal band in the "Requirement 2" requires improvements of the output signal band determined by the load resistance R and a parasitic capacitance C of the transistors composing the differential pairs 41 and 43, and of the through-rate determined by the next stage input load such as a gate capacitance with respect to a driving ability (bias current amount) of the differential pairs 41 and 43.
This means, in the circuit design, the increase of the bias current and the decrease in size of the transistors composing the differential pair, that is the increase of a current density between the drain and the source leads to the increase of the minimum potential V.sub.ds-min between the drain and the source required for the saturating operation, so that the limiter amplitude R.times.I.sub.s shown in Eq. (3) is also restricted in Eq. (25), thereby making the direct current design difficult.
Examples of general numerical values in Eq. (25) for a CMOS manufacturing process are shown in the following Table 1.
TABLE 1 Numerical value examples for CMOS manufacturing process ITEM SYMBOL VOLTAGE (V) REMARKS SOURCE V.sub.dd 3.0-5.0 3 V IN GENERAL VOLTAGE THRESHOLD V.sub.t 0.5-1.0 PROCESS MINIMUM VOLTAGE MEASUREMENT SATURATED V.sub.ds-min DESIGNED TO BE DEPENDENT ON DRAIN 1.0 OR BELOW CURRENT DENSITY SOURCE POTENTIAL
According to Table 1, supposing V.sub.dd =3V, V.sub.gs -V.sub.t =0.8V and V.sub.ds-min =0.4V in Eq. (25), the limiter amplitude R.times.I.sub.s requires to be 1V or less including the variation.
Accordingly, the limiter amplitudes will now be considered in case the current sources 1-3 shown in FIGS. 8-10 are used for a bias current I.sub.s of the differential pairs 41 shown in FIG. 11. Particularly for the analog linear amplification, it is important to enlarge the limiter amplitude in respect of securing the input dynamic range.
In the prior art shown in FIGS. 8-10, except for the contents to be suppressed as the objects of the current source in use, the values thereof vary greatly with the variations of the circumferential and manufacturing process conditions (variations of .DELTA..sub.r and .DELTA..sub.B).
The variation tendencies can be calculated by Eqs. (8), (9), (13), (14), (20), and (21) as shown in the following Table 2. Also, FIG. 12 shows a small signal gain variation characteristic as the resistance R is varied, FIG. 13 shows a small signal gain variation characteristic as the gain coefficient .beta. is varied, FIG. 14 shows a limiter amplitude variation characteristic as the resistance R is varied, and FIG. 15 shows a limiter amplitude variation characteristic as the gain coefficient .beta. is varied.
TABLE 2 .DELTA..sub.r and .DELTA..sub.B dependencies of small signal gain and limiter amplitude by current source types CURRENT SOURCE SMALL SIGNAL GAIN LIMITER AMPLITUDE TYPE VARIATION: G/G.sub.typ VARIATION: V/V.sub.typ CURRENT (1 .+-. .DELTA..sub.r) .times. (1 .+-. .DELTA..sub.b).sup.0.5 1 .+-. .DELTA..sub.r VARIATION SUPPRESSING TYPE 1 RESISTANCE (1 .+-. .DELTA..sub.r).sup.0.5 .times. (1 .+-. .DELTA..sub.B).sup.0.5 1 VARIATION SUPPRESSING TYPE 2 GAIN VARIATION 1 1/[(1 .+-. .DELTA..sub.r) .times. (1 .+-. .DELTA..sub.B)] SUPPRESSING TYPE 3
From the above, in the direct current design considering the variations of the circumferential and manufacturing process conditions, the maximum limiter amplitude at the time of condition variations is supposed to be R.times.I.sub.s in Eq. (25) as described above so that the limiter amplitude under the typical condition is made small by the amount of variation. Accordingly, it is found that the largest limiter amplitude can be secured when the resistance variation suppressing type current source 2 without limiter amplitude variations is used as the bias for the differential pair.
However, as described above, since the analog linear amplification has often an object of the separation of S/N or a faithful reproduction of the input, it is also important to suppress the small signal gain variation.
However, as shown in Table 2 and FIGS. 10-13, in case the current sources are independently used, it is not possible to suppress both of the small signal gain variation and the limiter amplitude variation, or to satisfy G/G.sub.typ =1 and V/V.sub.typ =1 at the same time against the variations of the circumferential and manufacturing process conditions. Therefore, it is to be urged to select an extreme improvement of one of the variations while worsening the variation of the other.
It has been possible in the prior art to secure the limiter amplitude even if the gain variation suppressing type current source 3 is solely used since the source voltage in use has been relatively high to the extent of 5V allowing a margin for the direct current design.
In a general circuit design, allowable values for design parameters are determined according to specification or the like. Also, in an amplifier design, an allowable gain variation .DELTA..sub.pg and an allowable limiter amplitude variation .DELTA..sub.pl can be calculated according to the design specification or the like, the allowable values depending on the place and object of the circuit.
If the current sources for different objects to be suppressed are independently used as in prior art, even though one of the variations of the gain and the limiter amplitude caused by the condition variations may have a margin with respect to the corresponding allowable variation, the other may not, which leads to the failure of the design proper.
As described above, in the design of the differential pair for the analog linear amplifier where the current sources for different objects to be suppressed, i.e. the limiter amplitude or the small signal gain, are independently used as in the prior art, there is a problem that it has become difficult to deal with the reduction of the source voltage following the minute machining of integrated circuits, the speedup of circuit operations, and the variations of circumferential and manufacturing process conditions in recent years, while enabling both of the design for suppressing the gain variation and the direct current design for securing the input dynamic range (limiter amplitude).